The present invention relates to a semiconductor device and a manufacturing method thereof. In particular, the invention relates to a semiconductor device having a gate electrode doped with B (boron) which can keep its characteristics stable even if in its manufacture a heating process is executed after formation of the gate electrode, and to a manufacturing method of such a semiconductor device. The invention also relates to a method of manufacturing a semiconductor device having a refractory metal gate electrode whose work function is controlled by the kind and the concentration of an impurity introduced.
It is known that the use of an SOI (silicon on insulator) structure facilitates complete insulation between devices and makes it possible to prevent a soft error and a latch-up phenomenon that is specific to CMOS transistors. On the other hand, studies to improve the operation speed and the reliability of CMOS transistor LSIs by using an SOI structure in which the thickness of a silicon active layer is about 500 nm have been made from the early stage of its development.
In recent years, it has become apparent that if conditions for depleting the almost entire silicon active layer (complete depletion type) are established by further thinning the silicon layer as the surface layer of an SOI structure to about 100 nm and controlling the impurity concentration of the channel to relatively low, even a superior performance can be obtained such as prevention of the short channel effect and improvement of the current driving ability of a MOS transistor.
However, where n.sup.+ polysilicon that has been widely used conventionally is used as a gate electrode material of an NMOS transistor, the impurity concentration of the channel should be made about 10.sup.17 cm.sup.-3 or more to set its threshold voltage Vth at about 0.5-1.0 V that is a threshold voltage value range of ordinary enhancement-type transistors. For this reason, to realize enhancement-type transistors while keeping them of a complete depletion type, studies of using p.sup.+ polysilicon (B-DOPOS (doped polysilicon)) as a gate material have been made in recent years.
On the other hand, in the field of bulk silicon devices that are now being miniaturized, because the use of only n-type polysilicon cannot make both n-channel and p-channel MOS transistors, a surface channel type transistor in which the short channel effect is less prone to occur, studies of a dual-gate process in which n.sup.+ polysilicon and p.sup.+ polysilicon are used for NMOS and PMOS transistors, respectively, have started with an intention of utilizing also the work function of the gate electrode to adjust the threshold voltage Vth.
FIG. 1A is a sectional view of a conventional semiconductor device, and FIG. 1B is an enlarged sectional view of a gate electrode and its vicinity (region A) of the semiconductor device of FIG. 1A. FIGS. 1A and 1B illustrate a problem that is caused by a manufacturing procedure when a heat treatment is performed after a p.sup.+ polysilicon gate electrode has been formed.
As shown in FIG. 1A, a LOCOS (local oxidation of silicon) oxide film 103 is formed for device isolation on the surface of a silicon substrate 101. Then, a gate electrode 105 of B-doped p.sup.+ polysilicon is formed on the silicon substrate 101 via a gate oxide film 102. Then, an interlayer insulating film 107 of SiO.sub.2 is formed on the gate electrode 105 and the silicon substrate 101.
Where B-doped p.sup.n+ polysilicon is used as the gate electrode 105, in a certain kind of heating process that is executed after the gate electrode 105 has been doped with B, B is introduced from the gate electrode 105 to the interlayer insulating film 107 (made of SiO.sub.2) precipitates therein (indicated by numeral 111 in FIG. 1B). Further, B diffuses into the interlayer insulating film 107 at relatively high speed (indicated by numeral 113 in FIG. 1B) As a result, the concentration of B in the p.sup.+ polysilicon gate electrode 105 decreases, whereby it may be depleted and in turn its work function may vary. It is a common understanding that the diffusion coefficient of B in the interlayer insulating film 107 is larger than that in the gate oxide film 102 even though both of them are made of SiO.sub.2, because the density of the interlayer insulating film 107 is lower than that of the gate oxide film 102.
Since the degree of diffusion 113 of B into the interlayer insulating film 107 varies with the temperature of the heating process, the variation in the work function of the gate electrode 105 has a dispersion. The characteristics such as Vth of a transistor having the gate electrode 105 that is made of p.sup.+ polysilicon come to have large dispersions.
It has become increasingly difficult to manufacture devices while keeping their characteristics stable by decreasing the above-described dispersions of the respective characteristics and the variation in the wafer surface of the work functions of p.sup.+ polysilicon gate electrodes. This is because of not only variations in the characteristics of a p.sup.+ polysilicon gate electrode as produced due to variations in a heating process that is executed after introducing an impurity into the gate electrode and a variation in the work function of p.sup.+ polysilicon due to a difference of the heating process employed in manufacture that is caused by a difference in the type of semiconductor device, but also an increased effective temperature variation in the wafer surface (particularly in recent years) due to employment of RTA (rapid thermal annealing) which tends to cause a large temperature variation, an increase in wafer diameter, and other factors.
As the work function of p.sup.+ polysilicon varies, Vth of transistors using it as a gate electrode varies in the wafer surface, which is a problem that will become more serious in manufacturing lower-voltage, lower-power-consumption semiconductor devices in the future. That is, if p.sup.+ polysilicon (B-DOPOS) is used as a gate material, Vth becomes about 1 V that is somewhat higher than a desired value in the case of a non-doped channel, which will be a problem in future devices in which the power supply voltage will be decreased to reduce the power consumption.
The above problems are not found only in the case of a gate electrode that is a single layer of p.sup.+ polysilicon that is doped with B, but found generally in the case of using a gate electrode that is doped with B that is an impurity having a large diffusion coefficient in SiO.sub.2. For example, those problems also occur in a W-polycide gate that is doped with B and WSi.sub.x single-layer gate that is doped with B. That is, where a refractory metal silicide is doped with such an impurity as B, even if a predetermined amount of B is introduced B concentration in a silicide as produced varies depending on the kind of subsequent heating process, because B has large diffusion coefficients in the silicide and SiO.sub.2 that is an insulating film usually surrounding a gate electrode. As a result, it is impossible to control, by only the B dose, the work function of a WSi.sub.x gate electrode as produced to a target value.
Studies have started to adjust Vth of a complete depletion type SOI transistor to a proper value by using a single layer of a refractory metal silicide such as WSi.sub.x Like WSi.sub.x, many refractory metal silicides have their work functions in the vicinity of the mid-gap energy of silicon. Where a refractory metal silicide is used as the gate electrode of a complete depletion type SOI transistor, in the case of a non-doped channel, the threshold voltage Vth has a proper value that is about 0.5 V in an NMOS transistor and about -0.5 V in a PMOS
It is known that where a refractory metal silicide such as WSi.sub.x or MoSi.sub.x is used as a gate electrode and its composition is made Si-rich as compared to the stoichiometric composition, its work function can be adjusted to some extent to the p.sup.+ silicon side by introducing B and to the n.sup.+ silicon side by introducing As as compared to the non-doped case.
As for the Vth control of transistors by a channel impurity, it has been pointed out that the Vth dispersion due to statistical fluctuation is increased as the transistors are miniaturized and the amount of an impurity contained in the channel of each transistor is decreased resultantly. Although this problem is not an urgent one unlike the case of the complete depletion type SOI transistor, a technique for solving this problem will be necessary in the future.
In the above-described circumstances, in the case of manufacturing a semiconductor device having a refractory metal silicide gate electrode whose work function is controlled, it is required to correctly control the threshold voltages Vth of various transistors of a semiconductor device to target values in such a manner that the threshold voltages Vth are made different from each other by changing the kind and the concentration of an impurity in ion implantation depending on the kind of transistor. That is, a proper semiconductor manufacturing method is required that does not vary the impurity concentration profile of a gate electrode after the ion implantation.